1. Technical Field of the Invention
The present invention relates to high-voltage inverter amplifier devices (or buffers), in particular those produced in the form of integrated circuits. The invention applies advantageously, but not exclusively, to plasma display panel (PDP) drivers.
2. Description of Related Art
A high-voltage inverter amplifier device receives as input a low-voltage logic signal (a logic signal whose low state is at 0 V for example and whose high state may typically be at about 3 V to 5 V) and delivers as output a high-voltage logic signal (the high state of which may be typically at about 50 V to 80 V).
Such a high-voltage amplifier device may operate in two different modes, namely a “direct current” mode (DC mode) and an “alternating current” mode (AC mode).
In DC mode, the supply voltage is fixed and equal to the voltage of the high-voltage logic. The change in state of the output of the amplifier device is therefore controlled by the change in state of the input signal.
In AC mode, the input signal is capable of adopting one of the two states of the low-voltage logic (low state at 0 V for example and high state at a voltage of 5 V, for example). The supply voltage then rises, for example from 0 V to 60 V in 200 nanoseconds and then stabilizes at this high voltage, for example for 400 nanoseconds, and then comes back down to 0 V. If the input signal is in the low state, the output voltage (output signal) must pass to the high state and it is therefore supposed to follow the supply voltage. If the input signal is at the high state, the output voltage remains in the low state.
A high-voltage inverter amplifier device of the prior art is shown schematically in FIG. 1. This device comprises vertical double-diffused MOS transistors (VDMOS transistors) capable of taking a high voltage between their source and their drain, for example 80 V, and having a low threshold voltage, typically of about 1.5 V, and transistors called 80VPCHFOX transistors, which are thick-gate-oxide high-voltage p-channel MOS transistors. These transistors have the advantage of being able to tolerate the entire supply voltage, for example up to 80 V, both between source and drain and on their gate, thereby allowing a level transposition to be made (low-voltage input logic transposed into high-voltage logic on the nodes A, B, C). However, these transistors have the disadvantage of possessing a high threshold voltage, typically of the order of 10 V.
As illustrated in FIG. 1, the device includes a level transposition cell connected to the input terminal IN and formed from the transistors M0, M2, M1 and M3. The device also includes an output stage comprising an 80VDMOS-type n-channel output transistor M28 equipped with a Zener diode Z1 anti-parallel connected between its source and its gate. The output stage also includes another transistor M6, also of the n-channel 80VDMOS type, connected between the source of the transistor M28 and a high-voltage earth/ground terminal VSSP. The common node between the transistors M6 and M28 forms the output terminal OUT of the device.
The inverter amplifier device also includes an intermediate stage, serving to drive the output stage, and composed here of an 80VPCHFOX-type p-channel transistor M5 and an 80VDMOS-type n-channel transistor M4. The gate of the transistor M5 is connected to the node B of the level transposition stage and the drain of the transistor M5 is connected to the drain of the transistor M4 and to the gate of the output transistor M28.
Let us now assume that the input voltage is in the low state in order to ensure a high logic level as output in AC mode. When the supply voltage VPP increases, the transistors M1, M3 and M5 can conduct only when the supply voltage VPP exceeds 10 V. Below this threshold, the voltage at the node C cannot rise and the output voltage cannot follow the supply voltage VPP. In other words, the output transistor M28 cannot conduct while the transistor M5 is not conducting.
When the transistor M5 starts to conduct, the voltage at the node C starts to rise and the output voltage then follows the supply voltage with a voltage shift equal to the threshold voltage of the transistor M5. The transistor M28 is fully conducting when its drain/source voltage difference has reached the threshold voltage of the transistor M5 increased by the Zener voltage of the diode Z1, which corresponds to an overall value of about 15 V. In other words, when the transistor M28 starts to conduct, it has a voltage on its terminals equal to 11.5 volts (threshold voltage of the transistor M5+threshold voltage of the transistor M28) and then equal to the full-conduction voltage shift of 15 V. Thus, the transistor M28 conducts the current with a high drain/source voltage difference. As a consequence, there is considerable power dissipation in the transistor M28, which is detrimental.
The present invention aims to provide a solution to this problem and other problems recognized by those skilled in the art.